1. Field of the Invention
This invention relates to a semiconductor device comprising an IIL (or I.sup.2 L, integrated injection logic) integrated with a vertical npn transistor and a vertical pnp transistor, and a method for its fabrication.
2. Description of the Prior Art
Conventional semiconductor devices can be exemplified by what is disclosed in Japanese Laid-open Patent Application No. 59-141261.
FIG. 11 illustrates a cross section of the structure of an IIL of this conventional semiconductor device. In FIG. 11, reference numeral 1 denotes a p-type semiconductor substrate; and 5, part of the emitter region of the IIL, which is an n.sup.+ -type buried layer formed at the same time as a collector buried layer of a vertical npn transistor. Reference numeral 6 denotes part of a separating region, which is a p.sup.+ -type buried layer formed at the same time as a collector buried layer of a vertical pnp transistor. Reference numeral 9 denotes an n.sup.- -type epitaxial layer, and 10 and 12 denote part of the separating region and part of the base region of the IIL, respectively, which are p.sup.- -type diffused layers formed at the same time as the collector region of the vertical pnp transistor. Reference numeral 14 denotes an n.sup.+ -type diffused layer that constitutes part of the emitter region of the IIL, and 17 and 18 denote an injector and part of the base region, respectively, of the IIL, which are p-type diffused layers formed at the same time as the base region of the vertical npn transistor. Reference numerals 20 and 110 denote a collector and part of the emitter region, respectively, of the IIL, which are n-type diffused layers formed at the same time as the base region of the vertical pnp transistor. Reference numeral 23 denotes a collector contact region of the IIL, which is an n.sup.+ -type diffused layer formed at the same time as the emitter region of the vertical npn transistor.
In the conventional semiconductor device constituted in this way, the p.sup.- -type diffused layer 12 serving as the base of the IIL is a diffused layer with a low impurity density formed at the same time as the collector region of the vertical pnp transistor, and hence an emitter injection efficiency can be made higher and current gain can be made greater.
Conventional semiconductor devices that have made the speed of IIL higher without causing a decrease in emitter-collector breakdown voltage can be exemplified by what is disclosed in Japanese Laid-open Patent Application No. 2-58865.
FIG. 12 illustrates a cross section of the structure of an IIL of this conventional semiconductor device. In FIG. 12, reference numeral 1 denotes a p-type semiconductor substrate; 4, an n.sup.+ -type buried layer serving as a collector buried layer of a vertical npn transistor; and 5, an n.sup.+ -type buried layer that constitutes part of the emitter region of the IIL, formed at the same time as the n.sup.+ -type buried layer 4. Reference numeral 6 denotes part of a separating region, which is a p.sup.+ -type buried layer; and 8, a p.sup.+ -type buried layer that constitutes part of the base region of the IIL, formed at the same time as the p.sup.+ -type buried layer 6. Reference numeral 9 denotes an n.sup.- -type epitaxial layer; 10, a p.sup.- -type diffused layer that constitutes part of the separating region; and 17 and 18 denote an injector and part of the base region, respectively, of the IIL, which are p-type diffused layers formed at the same time as the base region 16 of the vertical npn transistor. Reference numerals 24 and 111 denote an emitter contact region and a collector region, respectively, of the IIL, which are n.sup.+ -type diffused layers formed at the same time as the emitter region 21 and collector contact region 22 of the vertical npn transistor. Reference numeral 112 denotes a p-type diffused layer that constitutes part of the base region of the IIL; and 113, an n.sup.+ -type diffused layer that constitutes part of the emitter region of the IIL.
In the conventional semiconductor device constituted in this way, the base of the IIL is formed by the p.sup.+ -type buried layer 8 and the p-type diffused layer 112, and hence the speed of IIL can be made higher without causing a decrease in emitter-collector breakdown voltage.
However, in such conventional semiconductor devices, for example, the semiconductor device disclosed in Japanese Laid-open Patent Application No. 59-141261, the emitter of IIL with which the p.sup.- -type diffused layer 12 comes into contact is the epitaxial layer having a lower impurity density than the p.sup.- -type diffused layer 12, and hence it is impossible to greatly improve the current gain. In addition, when the epitaxial layer 9 is made thin so that the speed and compactness of the device can be made higher, the depth of the p.sup.- -type diffused layer 12 must be made smaller as a matter of course, which results in a small width of the base of IIL to bring about a state of punch-through between the collector and emitter at a low voltage, resulting in no normal operation of the IIL. On the other hand, making the p.sup.- -type diffused layer 12 have a high impurity density in order to avoid such a difficulty brings about a decrease in the current gain and also an increase in the impurity density at the collector region of the vertical pnp transistor, formed at the same time as the p.sup.- -type diffused layer 12, resulting in a lowering of the Early voltage. This semiconductor device has been involved in such problems.
In the semiconductor device disclosed in Japanese Laid-open Patent Application No. 2-58865, the collector region 111 of the IIL is formed at the same time as the emitter region 21 of the vertical npn transistor, and hence, in order to maintain the characteristics of the vertical npn transistor, the depth of junction can not be made so much large, and the width of the base of IIL right beneath the collector region 111 can not be made small. Thus this semiconductor device also has had the problem that there is a limit to the improvement in the current gain or achievement of a higher speed of IIL.